The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a technique effectively applied to the manufacture of a semiconductor element with a metal silicide layer.
With increasing integration of semiconductor devices, metal insulator semiconductor field effect transistors (MISFETs) have been microfabricated according to a scaling rule. However, since a gate resistance or a source/drain resistance is increased, even if the MISFET is microfabricated, a high-speed operation cannot be disadvantageously obtained. Thus, a salicide (self-aligned silicide) technique has been studied which is designed to decrease the resistance of a gate or source/drain by forming a low-resistance metal silicide layer, for example, a nickel silicide layer or a cobalt silicide layer, by a self-alignment process on the surface of a conductive film forming the gate and on the surface of a semiconductor region forming the source/drain.
Japanese Unexamined Patent Publication No. 2008-78559 (Patent Document 1) discloses a technique for forming a nickel platinum monosilicide layer.
Japanese Unexamined Patent Publication No. Hei 11 (1999)-251591 (Patent Document 2) discloses a technique that can make the thickness of a silicide layer formed at an edge of a silicon electrode substantially equal to that at the center of the electrode.
Japanese Unexamined Patent Publication No. 2008-103644 (Patent Document 3) discloses a technique regarding formation of a nickel silicide layer.    [Patent Document 1]    Japanese Unexamined Patent Publication No. 2008-78559    [Patent Document 2]    Japanese Unexamined Patent Publication No. Hei 11 (1999)-251591    [Patent Document 3]    Japanese Unexamined Patent Publication No. 2008-103644